Quantum security in every pocket.

We develop quantum random-number generators in standard CMOS silicon.

Explore chip and IP integration

VERA-Q USB quantum entropy kit in its aluminium housing
VERA-Q quantum entropy kit. Evaluation through shortlist access.

From your desk to every chip.

Bring quantum entropy onto your board with a QRNG chip, or inside your own silicon with entropy-cell IP.

Every key starts with entropy.

Passwords, keys, signatures and session tokens all begin with random numbers. If those numbers can be predicted, the cryptography on top fails, however strong it is.

Post-quantum cryptography replaces the algorithms. It does not fix weak randomness underneath. And the deadlines are set: the EU asks member states to begin the post-quantum transition by the end of 2026 and to protect high-risk systems by 2030.

Quantum noise in silicon. No light source.

Inside a deliberately leaky junction of a standard CMOS chip, single electrons cross at moments that physics makes unpredictable. We count them.

That quantum noise becomes random numbers, checked by continuous health tests. No laser, no LED, no optics: just silicon.

Illustration of an array of quantum entropy cells
Illustration

Latest

Building a sensor test setup?

Explore ETRA acquisition, timing and FPGA processing, with TEC X8 temperature control for sensors and photonic chips.

Built with Europe's quantum and chips programmes.

Q-PLANET

The European neutral-atom quantum-computing pilot line coordinated by Pasqal, in which iQrypto participates.

SPIN-CHIP

Chips JU project coordinated by Thales Research & Technology, on spintronic devices and quantum entropy.

REACT

MSCA doctoral network. We are bringing quantum entropy into a secure RISC-V system.

Research and partners

Bring quantum entropy into your product.

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