iQrypto / Engineering
Control, timing and readout for sensors and quantum hardware.
We built the electronics to prove our own quantum chip. Now we build them for you, on one platform: ETRA.
The ETRA platform
- Up to 64 channels at up to 2 Gbps per lane in our newest architecture
- FPGA processing on Zynq UltraScale+, so the host receives results, not raw data
- Ten programmable rails and eight 24-bit voltage or current channels, monitored continuously
- SFP+ and QuadSFP+ links out. GUI, Python plugins, TCP and Linux APIs.
- In paid industrial use at automotive and railway customers
Image sensor test system engineering
One test backbone, from the bench to the wafer.
Bench boxes and probe-card electronics run on the same ETRA hardware, so firmware, recipes and data formats carry straight from bench to wafer.
We have demonstrated visible CMOS sensors (Full HD at 3,000 fps over LVDS), quantum dots on CMOS (500 fps), SiGe SWIR devices and imaging ROICs, with in-FPGA processing such as centre of gravity during readout. The same approach applies to InGaAs SWIR, SPAD and time-of-flight, event-based, hyperspectral, thermal IR and X-ray detectors.
Then it is one step to a camera: the timing, firmware and calibration proven in test carry over to a compact camera design.
Quantum and high-speed electronics
Drive, time and read out quantum and photonic chips.
Electro-optic modulator drive with bit patterns on up to 64 lanes at 2 Gbps. Quiet bias for phase shifters. Nanosecond-level synchronisation of control and acquisition. Readout with processing in the FPGA.
Our quantum-computing research includes participation in Q-PLANET, a European neutral-atom quantum pilot line coordinated by Pasqal.
TEC X8
Temperature control for sensors and photonic chips: eight Peltier outputs, four Pt100 inputs and a REST API.