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A Reconfigurable 10 ns Resolution, Wide Range FPGA-Based Timing Generator for CMOS Image Sensors

An IWASI 2025 paper on reconfigurable FPGA timing for CMOS image-sensor characterization, with measured results and the author's manuscript available as a PDF.

FPGACMOS image sensorstiming controlscientific papers
iQrypto author-version cover for the IWASI 2025 paper on an FPGA-based timing generator for CMOS image sensors

Paper details

2025 10th International Workshop on Advances in Sensors and Interfaces (IWASI)

Published 3 Jul 2025. Pages 1-5.

DOI: 10.1109/iwasi66786.2025.11121973

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6 pages including the iQrypto cover. The original paper follows unchanged.

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Abstract

CMOS image sensors are now ubiquitous across automotive, security, consumer and scientific markets. CMOS pixels, are sensitive to timing variations, thereby highlighting the need to carefully characterize their performance. In this context, reconfigurable architectures such as FPGA-based systems, offer a solid and flexible electronic platform to design the needed timing waveforms for pixel characterization. In a typical 4T pixel architecture, the transfer gate transistor is most sensitive to variations in rise/fall time edges and voltage because of the charge transfer mechanisms needed to transfer the charge from the photodiode to the floating diffusion. The ability to correctly set up the pulse’s duration and resolution is therefore crucial for precise measurement of pixel parameters. In this paper, we use a simple three-register reconfigurable architecture that modulates the pixel control signal timings. Experimental results demonstrate that by using a commercial Xilinx Zynq-7020 architecture it is possible to reach a 10 ns resolution while keeping a reconfigurable timing up to almost 43 s for precise characterization of the CMOS pixels. Such approach is particularly useful for characterizing transfer gate signals and the sensor dark current where the combination of precision and long exposure times is needed.

What the paper covers

The paper presents a three-register FPGA architecture for controlling CMOS image-sensor pixel timing. Delay, high and low intervals can be reconfigured at run time, supporting both short control pulses and long integration windows for characterization.

The reported implementation uses a Xilinx Zynq-7020 and a 100 MHz timing clock. The study reports a timing resolution of 10 ns and a configurable range up to approximately 42.95 seconds. These are results for the setup described in the paper, including its signal-driving circuitry and sensor load.

Scope of the measurements

The paper reports measured pulse shapes and explains how the external load affects rise time, fall time and the voltage reached by the shortest pulses. The results should be read with those conditions and limitations, rather than treated as a specification for every sensor or electronics configuration.

The download contains the author’s pre-publication manuscript with an iQrypto cover; it is not the IEEE version of record. Copyright 2025 IEEE. Personal use is permitted; redistribution, republication and other reuse require IEEE’s permission, as stated on the cover. The five original manuscript pages, figures and references are retained unchanged. Use the DOI for the published version.

For the related platform and current integration options, explore ETRA acquisition and control or discuss an image-sensor test project.

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