When the entropy source sits inside the chip that uses it, random numbers never travel over an external bus that can be probed. There is no extra part on the board, no extra package and no extra power rail.
The same quantum cell that powers our chip becomes a hard-IP block small enough for a microcontroller. A full die serves high-throughput systems.
Talk to us if you design processors or secure chips and want quantum entropy in your own silicon.
Compare the engineering work involved in USB, packaged-chip and IP evaluation in our QRNG integration-path guide.
Specifications
- Block size
- 100 × 100 µm for an IoT-class integration block
- Cell size
- Under 5 µm
- Cell power
- Under 1 nW on average, cell only
- Scales with
- Cells run in parallel. You size the block to your throughput.
- Target devices
- MCUs, RISC-V cores and secure SoCs
- Integration work
- Secure RISC-V demonstration through the REACT doctoral network
Discuss your IP integration.
Share your target process, device constraints and entropy requirements.